The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent that it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Integrated circuits (ICs), such as application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other ICs are often composed of standard cells. The cells (also referred to herein as “logic cells”) are standard in the sense that the cells are of standard size(s) and the cells have certain standard logic characteristics. Logic cells may include memory cells, flip flops, or latches, or they may include logic functionality such as NAND and NOR gates. In conventional ICs, the standard cells are arranged in a grid pattern (a series of columns and rows along a plane of the IC with one or more metal layers overlaid on top of the plane to provide electrical connectivity between the logic cells as well as to provide power to the logic cells.
Design for Rule Checking (DRC) design rules include rules related to spacing between two adjacent objects, such as standard cells, in an IC. In one example, a given cell is required by DRC constraints to be no closer than a minimum distance from a voltage rail of the IC. This DRC constraint prevents the voltage rail from interfering with operation of the given cell. An alternative DRC constraint enables a cell to be adjacent to or to overlap with a voltage rail as long as metal portions of the cell are within a certain minimum distance from the voltage rail. In either case, this DRC constraint results in portions of the IC being unusable, and thus wasted space.
Tap cells and spare cells are introduced into the circuit during the design phase. Tap cells provide well tap connectivity and substrate tap connectivity to transistors in logic cells. Well tap connectivity provides positive voltage, for example, to N-type wells of a CMOS transistor, and substrate connectivity provides negative or ground voltage to a substrate region (such as a P-type substrate region) of the transistors. Well taps and substrate taps lower the resistance of the substrate, thereby preventing shorts.
Spare cells include spare logic portions. Early in a design process, inputs of the spare logic cell are typically tied to negative or ground voltage, or in some other known state, and outputs of the spare logic cell are left floating, or left in some other known state. Later in the design process, metal traces may be added to connect the spare logic cell to other cells in the IC in order to fix a bug or flaw. Placing spare cells into the design enables a chip designer to address bugs or flaws in the design more easily than having to add new logic cells to the design to address bugs or flaws at a later stage in the design process.